TSMC Roadmap Details 3nm & 2nm Process Technologies: N3E, N3P, N3X, N2P, N2X

By: Jason R. Wilson
Source: https://wccftech.com/tsmc-roadmap-details-3nm-2nm-process-technologies-n3e-n3p-n3x-n2p-n2x/

Taiwan Semiconductor Co. (TSMC) showcased its newest process technology advancements which include 3nm and 2nm nodes.

TSMC debuts enhanced N3P 3nm Process, HPC-Focused N3X Process, N3AE Auto Early Program, and updates 2nm and TSMC 3DFabric Progress

During the talks, the company divulged its progress in 2nm process technology and new partners for the company’s current 3nm technology, which will offer a more extensive range of process technologies that will be able to meet broader audience demand. Included in the technological advances are N3P, N3X, and N3AE. Additionally, the company discussed its 2nm goals and 3DFabric progression.

The new process technologies from TSMC will offer more for HPC and automotive applications while offering more power and performance.

  • N3P – an enhanced 3nm process for increased power, performance, and density.
  • N3X – a process focused on high-performance computing (HPC) applications.
  • N3AE – an introduction to automotive applications using the most advanced silicon technology.

The North America Technology Symposium supplies over 1,600 customers and partners registered to attend. It is the first of the TSMC’s Technology Symposiums worldwide that are rolling out over the next several months. The North American symposium also showcases an Innovation Zone spotlighting eighteen emerging start-ups’ compelling technologies.

Our customers never stop finding new ways to harness the power of silicon to create innovations that shall amaze the world for a better future. In the same spirit, TSMC never stands still, and we keep enhancing and advancing our process technologies with more performance, power efficiency, and functionality so their pipeline of innovation can continue flowing for many years to come.

— Dr. C.C. Wei, TSMC CEO

Key technologies highlighted at the North America Technology Symposium include:

Broader 3nm Portfolio, including N3P, N3X, and N3AE – Now that 3nm technology is in volume production and the N3 process and N3E version are on the way during 2023, the company is adding new variations to its roadmap to meet the diverse demands of its clients.

  • N3P, scheduled to enter production in the second half of 2024, offers an additional boost to N3E with 5% more speed at the same leakage, 5-10% power reduction at the same rate, and 1.04X more chip density.
  • N3X, which prioritizes performance and maximum clock frequencies for HPC applications, provides 5% more speed versus N3P at a drive voltage of 1.2V, with the same improved chip density as N3P, and will enter volume production in 2025.
  • N3AE, or “Auto Early,” available in 2023, offers automotive process design kits (PDKs) based on N3E and allows customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025.

2nm Technology Making Solid Progress – TSMC is still developing the 2nm technology, which employs nanosheet transistors and is progressing in yield and device performance. The company is focused on releasing the new technology in 2025. It will provide up to fifteen percent improvement in speed over N3E at the same power while offering a thirty percent reduction in power and a more significant chip density at 1.15X.

Pushing the Limits of CMOS RF Technology with N4PRF – TSMC is also developing N4PRF, which is expected to be the industry’s most advanced CMOS radio frequency technology for digital-intensive RF applications such as WiFi 7 RF system-on-chip. The new N4PRF will support 1.77X increased logic density and forty-five percent reduced power in logic while maintaining the same speed as N6RF, which was introduced in 2021.

TSMC 3DFabric Advanced Packaging and Silicon Stacking – Major new developments in TSMC’s 3DFabric system integration technologies include:

  • Advanced Packaging – To support the demands of HPC applications to fit more processors and memory in a single package, TSMC is developing Chip on Wafer on Substrate (CoWoS) solution with up to 6 times reticle-size (~5,000mm2) RDL interposer, capable of accommodating 12 stacks of HBM memory.
  • 3D Chip Stacking – TSMC announced SoIC-P, microbump versions of its System on Integrated Chips (SoIC) solutions providing a cost-effective way for 3D chip stacking. SoIC-P complements TSMC’s existing bumpless solutions for high-performance computing (HPC) applications, now known as SoIC-X.
  • Design Support – TSMC introduced 3Dblox 1.5, the newest version of its open standard design language, to lower the barriers to 3D IC design. 3Dblox 1.5 adds automated bump synthesis, helping designers deal with the complexities of large dies with thousands of bumps and potentially reducing design times by months.
Written by Jason R. Wilson